1. Field of the Invention
The present invention relates to fabrication techniques for integrated circuit elements and, in particular, to a process flow for fabricating a MOSFET that utilizes raised source/drain contacts formed entirely over isolation oxide.
2. Discussion of the Related Art
FIG. 1 shows a conventional MOSFET transistor 10 fabricated in an active device region of a semiconductor wafer substrate, the active device region being defined by field oxide regions. In fabricating the MOSFET 10, a layer of polysilicon is formed on a layer of thin oxide that is formed on the substrate active device region. The polysilicon layer is then masked and both the exposed polysilicon and the underlying thin oxide are etched to define a polysilicon gate region 12 separated from the substrate by thin gate oxide 14. A self-aligned implant of N-type dopant then forms lightly doped diffusion (LDD) source/drain regions in the substrate as a first phase in forming the substrate N+ source/drain regions of the MOSFET. After the formation of oxide sidewall spacers (SWS) 15 on the sidewalls of the polysilicon gate 12 and the gate oxide 14, a second N+ implant is performed to set the conductivity of the gate region 12 to a desired level and to complete the N+ source/drain regions 16. Titanium is then deposited on the exposed upper surfaces of the N+ source/drain regions 16 and the polysilicon gate region 12 and annealed, thereby causing the titanium to react with the underlying N+ silicon of the substrate source/drain regions 16 and the doped polysilicon gate 12 to form titanium salicide 18 on these surfaces. A layer of dielectric material 20, typically silicon oxide, is then formed, contact openings are etched in the dielectric 20, and a metallization layer 22 is formed to provide contacts to the salicide 18 on the source/drain regions 16 and on the polysilicon gate 12.
The above-described MOSFET fabrication technique suffers from potential problems in the formation of source/drain regions 16. First, selective growth of the salicide needed for good contacts with the metallization layer requires a reaction between the titanium and underlying silicon. Therefore, the titanium must be formed on the N+ source/drain regions 16, which must be wide enough to accommodate the photolithographic limitations of the contact opening; this results in a wider device. Also, since silicon is consumed in the process, the junction depth of the N+ source/drain regions 16 is difficult to control and dopant depletion can occur in these regions. Furthermore, formation of the deep, heavily-doped N+ junction for the source/drain regions 16 can result in dopant diffusion under the gate region, thereby reducing the effective channel length of the MOSFET, i.e., the so-called "short channel effect." Also, due to the poor selectivity between the salicide and the oxide, the salicide may be removed during the contact etch process, leading to contact resistance and leakage current problems.